diff --git a/src/Ryujinx.Cpu/AddressTable.cs b/src/Ryujinx.Cpu/AddressTable.cs
index 4015e0801..5dc72a7c8 100644
--- a/src/Ryujinx.Cpu/AddressTable.cs
+++ b/src/Ryujinx.Cpu/AddressTable.cs
@@ -49,7 +49,7 @@ namespace ARMeilleure.Common
 
             public TableSparseBlock(ulong size, Action<IntPtr> ensureMapped, PageInitDelegate pageInit)
             {
-                SparseMemoryBlock block = new SparseMemoryBlock(size, pageInit, null);
+                SparseMemoryBlock block = new(size, pageInit, null);
 
                 _trackingEvent = (ulong address, ulong size, bool write) =>
                 {
@@ -363,7 +363,7 @@ namespace ARMeilleure.Common
         /// <returns>The new sparse block that was added</returns>
         private TableSparseBlock ReserveNewSparseBlock()
         {
-            TableSparseBlock block = new TableSparseBlock(_sparseBlockSize, EnsureMapped, InitLeafPage);
+            TableSparseBlock block = new(_sparseBlockSize, EnsureMapped, InitLeafPage);
 
             _sparseReserved.Add(block);
             _sparseReservedOffset = 0;
@@ -416,7 +416,7 @@ namespace ARMeilleure.Common
                 IntPtr address = (IntPtr)NativeAllocator.Instance.Allocate((uint)size);
                 page = new AddressTablePage(false, address);
 
-                Span<T> span = new Span<T>((void*)page.Address, length);
+                Span<T> span = new((void*)page.Address, length);
                 span.Fill(fill);
             }
 
diff --git a/src/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs b/src/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
index 146805982..308e5f0d2 100644
--- a/src/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
+++ b/src/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
@@ -340,7 +340,7 @@ namespace Ryujinx.Cpu.Jit
         {
             int pages = GetPagesCount(va, (uint)size, out va);
 
-            List<MemoryRange> regions = new List<MemoryRange>();
+            List<MemoryRange> regions = new();
 
             ulong regionStart = GetPhysicalAddressChecked(va);
             ulong regionSize = PageSize;
diff --git a/src/Ryujinx.Cpu/Jit/MemoryManagerHostTracked.cs b/src/Ryujinx.Cpu/Jit/MemoryManagerHostTracked.cs
index d802f5046..98b00ca0b 100644
--- a/src/Ryujinx.Cpu/Jit/MemoryManagerHostTracked.cs
+++ b/src/Ryujinx.Cpu/Jit/MemoryManagerHostTracked.cs
@@ -443,7 +443,7 @@ namespace Ryujinx.Cpu.Jit
                 return null;
             }
 
-            List<HostMemoryRange> regions = new List<HostMemoryRange>();
+            List<HostMemoryRange> regions = new();
             ulong endVa = va + size;
 
             try
diff --git a/src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs b/src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
index 340ae43d1..fb30be2b6 100644
--- a/src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
+++ b/src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
@@ -342,7 +342,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
 
         public readonly void Cset(Operand rd, ArmCondition condition)
         {
-            Operand zr = new Operand(ZrRegister, RegisterType.Integer, rd.Type);
+            Operand zr = new(ZrRegister, RegisterType.Integer, rd.Type);
             Csinc(rd, zr, zr, (ArmCondition)((int)condition ^ 1));
         }
 
@@ -857,7 +857,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
 
         public readonly void PrfmI(Operand rn, int imm, uint type, uint target, uint policy)
         {
-            Operand rt = new Operand((int)EncodeTypeTargetPolicy(type, target, policy), RegisterType.Integer, OperandType.I32);
+            Operand rt = new((int)EncodeTypeTargetPolicy(type, target, policy), RegisterType.Integer, OperandType.I32);
             WriteInstruction(0xf9800000u | (EncodeUImm12(imm, 3) << 10), rt, rn);
         }
 
@@ -868,7 +868,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
 
         public readonly void Prfum(Operand rn, int imm, uint type, uint target, uint policy)
         {
-            Operand rt = new Operand((int)EncodeTypeTargetPolicy(type, target, policy), RegisterType.Integer, OperandType.I32);
+            Operand rt = new((int)EncodeTypeTargetPolicy(type, target, policy), RegisterType.Integer, OperandType.I32);
             WriteInstruction(0xf8800000u | (EncodeSImm9(imm) << 12), rt, rn);
         }
 
diff --git a/src/Ryujinx.Cpu/PrivateMemoryAllocator.cs b/src/Ryujinx.Cpu/PrivateMemoryAllocator.cs
index 99528b576..6ed3be524 100644
--- a/src/Ryujinx.Cpu/PrivateMemoryAllocator.cs
+++ b/src/Ryujinx.Cpu/PrivateMemoryAllocator.cs
@@ -40,7 +40,7 @@ namespace Ryujinx.Cpu
                 Size = size;
                 _freeRanges = new List<Range>
                 {
-                    new Range(0, size),
+                    new(0, size),
                 };
             }
 
@@ -84,7 +84,7 @@ namespace Ryujinx.Cpu
 
             private void InsertFreeRange(ulong offset, ulong size)
             {
-                Range range = new Range(offset, size);
+                Range range = new(offset, size);
                 int index = _freeRanges.BinarySearch(range);
                 if (index < 0)
                 {
@@ -97,7 +97,7 @@ namespace Ryujinx.Cpu
             private void InsertFreeRangeComingled(ulong offset, ulong size)
             {
                 ulong endOffset = offset + size;
-                Range range = new Range(offset, size);
+                Range range = new(offset, size);
                 int index = _freeRanges.BinarySearch(range);
                 if (index < 0)
                 {
@@ -214,7 +214,7 @@ namespace Ryujinx.Cpu
 
             ulong blockAlignedSize = BitUtils.AlignUp(size, _blockAlignment);
 
-            MemoryBlock memory = new MemoryBlock(blockAlignedSize, _allocationFlags);
+            MemoryBlock memory = new(blockAlignedSize, _allocationFlags);
             T newBlock = createBlock(memory, blockAlignedSize);
 
             InsertBlock(newBlock);