mirrors/Citron
1
0
Fork 0
mirror of https://git.citron-emu.org/Citron/Citron.git synced 2025-03-15 06:44:48 +00:00
Code Issues Projects Releases 1 Packages Wiki Activity Actions

service/nvdrv: Implement NVGPU_GPU_IOCTL_NUM_VSMS

Browse source 
- Add IoctlNumVsms struct definition
- Implement ioctl 0x13 to return number of SM units (2 for Tegra X1)
This commit is contained in:
Zephyron 2025-02-09 11:43:08 +10:00
parent 384a18927b
commit 6e16a8db1c
No known key found for this signature in database
2 changed files with 23 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
View file

@ -74,9 +74,23 @@ NvResult nvhost_ctrl_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8>
case 0x6:
return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output,
inline_output);
case 0x13:
LOG_DEBUG(Service_NVDRV, "(STUBBED) called.");
return NvResult::NotImplemented;
case 0x13: {
// NVGPU_GPU_IOCTL_NUM_VSMS
struct Parameters {
u32 num_vsms; // Output: number of SM units
u32 reserved; // Output: reserved/padding
};
static_assert(sizeof(Parameters) == 8, "Parameters is incorrect size");
// The Tegra X1 used in Switch has 2 SM units
Parameters params{
.num_vsms = 2,
.reserved = 0
};
std::memcpy(output.data(), &params, sizeof(Parameters));
return NvResult::Success;
}
default:
break;
}

8
src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h
View file

@ -200,6 +200,12 @@ private:
};
static_assert(sizeof(IoctlGetGpuTime) == 0x10, "IoctlGetGpuTime is incorrect size");
struct IoctlNumVsms {
u32_le num_vsms; // Output: number of SM units
u32_le reserved; // Output: reserved/padding
};
static_assert(sizeof(IoctlNumVsms) == 8, "IoctlNumVsms is incorrect size");
NvResult GetCharacteristics1(IoctlCharacteristics& params);
NvResult GetCharacteristics3(IoctlCharacteristics& params,
std::span<IoctlGpuCharacteristics> gpu_characteristics);
@ -208,8 +214,6 @@ private:
NvResult GetTpcMasks2(IoctlGetTpcMasks& params);
NvResult GetTPCMasks3(IoctlGpuGetTpcMasksArgs& params, std::span<u32> tpc_mask);
NvResult GetActiveSlotMask(IoctlActiveSlotMask& params);
NvResult ZCullGetCtxSize(IoctlZcullGetCtxSize& params);
NvResult ZCullGetInfo(IoctlNvgpuGpuZcullGetInfoArgs& params);