service/nvdrv: Implement NVGPU_GPU_IOCTL_NUM_VSMS

- Add IoctlNumVsms struct definition
- Implement ioctl 0x13 to return number of SM units (2 for Tegra X1)

src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp

@@ -74,9 +74,23 @@ NvResult nvhost_ctrl_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8>
         case 0x6:
             return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output,
                                    inline_output);
-        case 0x13:
+        case 0x13: {
-            LOG_DEBUG(Service_NVDRV, "(STUBBED) called.");
+            // NVGPU_GPU_IOCTL_NUM_VSMS
-            return NvResult::NotImplemented;
+            struct Parameters {
+                u32 num_vsms;     // Output: number of SM units
+                u32 reserved;     // Output: reserved/padding
+            };
+            static_assert(sizeof(Parameters) == 8, "Parameters is incorrect size");
+
+            // The Tegra X1 used in Switch has 2 SM units
+            Parameters params{
+                .num_vsms = 2,
+                .reserved = 0
+            };
+
+            std::memcpy(output.data(), &params, sizeof(Parameters));
+            return NvResult::Success;
+        }
         default:
             break;
         }

src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h

@@ -200,6 +200,12 @@ private:
     };
     static_assert(sizeof(IoctlGetGpuTime) == 0x10, "IoctlGetGpuTime is incorrect size");
 
+    struct IoctlNumVsms {
+        u32_le num_vsms;    // Output: number of SM units
+        u32_le reserved;    // Output: reserved/padding
+    };
+    static_assert(sizeof(IoctlNumVsms) == 8, "IoctlNumVsms is incorrect size");
+
     NvResult GetCharacteristics1(IoctlCharacteristics& params);
     NvResult GetCharacteristics3(IoctlCharacteristics& params,
                                  std::span<IoctlGpuCharacteristics> gpu_characteristics);
@@ -208,8 +214,6 @@ private:
     NvResult GetTpcMasks2(IoctlGetTpcMasks& params);
     NvResult GetTPCMasks3(IoctlGpuGetTpcMasksArgs& params, std::span<u32> tpc_mask);
 
-
-
     NvResult GetActiveSlotMask(IoctlActiveSlotMask& params);
     NvResult ZCullGetCtxSize(IoctlZcullGetCtxSize& params);
     NvResult ZCullGetInfo(IoctlNvgpuGpuZcullGetInfoArgs& params);