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service/nvdrv: Implement NVGPU_GPU_IOCTL_NUM_VSMS
- Add IoctlNumVsms struct definition - Implement ioctl 0x13 to return number of SM units (2 for Tegra X1)
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384a18927b
commit
6e16a8db1c
2 changed files with 23 additions and 5 deletions
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@ -74,9 +74,23 @@ NvResult nvhost_ctrl_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8>
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case 0x6:
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case 0x6:
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return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output,
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return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output,
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inline_output);
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inline_output);
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case 0x13:
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case 0x13: {
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LOG_DEBUG(Service_NVDRV, "(STUBBED) called.");
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// NVGPU_GPU_IOCTL_NUM_VSMS
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return NvResult::NotImplemented;
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struct Parameters {
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u32 num_vsms; // Output: number of SM units
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u32 reserved; // Output: reserved/padding
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};
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static_assert(sizeof(Parameters) == 8, "Parameters is incorrect size");
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// The Tegra X1 used in Switch has 2 SM units
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Parameters params{
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.num_vsms = 2,
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.reserved = 0
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};
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std::memcpy(output.data(), ¶ms, sizeof(Parameters));
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return NvResult::Success;
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}
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default:
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default:
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break;
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break;
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}
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}
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@ -200,6 +200,12 @@ private:
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};
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};
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static_assert(sizeof(IoctlGetGpuTime) == 0x10, "IoctlGetGpuTime is incorrect size");
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static_assert(sizeof(IoctlGetGpuTime) == 0x10, "IoctlGetGpuTime is incorrect size");
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struct IoctlNumVsms {
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u32_le num_vsms; // Output: number of SM units
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u32_le reserved; // Output: reserved/padding
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};
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static_assert(sizeof(IoctlNumVsms) == 8, "IoctlNumVsms is incorrect size");
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NvResult GetCharacteristics1(IoctlCharacteristics& params);
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NvResult GetCharacteristics1(IoctlCharacteristics& params);
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NvResult GetCharacteristics3(IoctlCharacteristics& params,
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NvResult GetCharacteristics3(IoctlCharacteristics& params,
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std::span<IoctlGpuCharacteristics> gpu_characteristics);
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std::span<IoctlGpuCharacteristics> gpu_characteristics);
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@ -208,8 +214,6 @@ private:
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NvResult GetTpcMasks2(IoctlGetTpcMasks& params);
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NvResult GetTpcMasks2(IoctlGetTpcMasks& params);
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NvResult GetTPCMasks3(IoctlGpuGetTpcMasksArgs& params, std::span<u32> tpc_mask);
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NvResult GetTPCMasks3(IoctlGpuGetTpcMasksArgs& params, std::span<u32> tpc_mask);
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NvResult GetActiveSlotMask(IoctlActiveSlotMask& params);
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NvResult GetActiveSlotMask(IoctlActiveSlotMask& params);
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NvResult ZCullGetCtxSize(IoctlZcullGetCtxSize& params);
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NvResult ZCullGetCtxSize(IoctlZcullGetCtxSize& params);
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NvResult ZCullGetInfo(IoctlNvgpuGpuZcullGetInfoArgs& params);
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NvResult ZCullGetInfo(IoctlNvgpuGpuZcullGetInfoArgs& params);
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